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general description the maxq611 is a low-power, 16-bit maxq ? micro - controller designed for low-power applications including universal remote controls, consumer electronics, and white goods. the device combines a powerful 16-bit risc microcontroller and integrated peripherals includ - ing two universal synchronous/asynchronous receiver- transmitters (usart), spi master/slave and i 2 c communications ports, along with an ir module with carrier frequency generation and flexible port i/o capable of multiplexed keypad control. the device provides 80kb of flash memory and 2kb of data sram. for the ultimate in low-power battery-operated performance, the device includes an ultra-low-power stop mode. in this mode, the minimum amount of circuitry is powered. wake-up sources include external interrupts, the power-fail interrupt, and a timer interrupt. applications universal remote controls for tablets universal remote controls for smartphones beneits and features fast, compact architecture allows easy integration into applications ? internal 12mhz oscillator requires no external components ? eficient, 16-bit maxq20s risc core ? 1.7v to 3.6v wide operating range ? 80kb flash program memory ? 2kb sram for data storage ? default v pfw compatible with maxq610 integrated ir module reduces cost and development time ? transmit and receive (code learning) modes ? automatic carrier generation/modulation ? glitch filter improves noise immunity ? conigurable high-current driver peripherals support multiple applications ? up to 32 (tqfn) or 38 (bare die) gpio ? two 16-bit programmable timers/counters include capture/compare functionality ? spi, i 2 c, and two usart busses ? programmable watchdog timer enhances system stability low power consumption maximizes battery life ? power-fail warning circuit minimizes effects of power fluctuation ? power-on and brownout reset circuitry ? 0.15a (typ), 2.0a (max) in stop mode, t a = +25c, power-fail monitor disabled ? 2.0ma (typ) at 12mhz in active mode ordering information/selector guide appears at end of data sheet. maxq is a registered trademark of maxim integrated products, inc.19-7309; rev 1; 12/14 16-bit maxq risc cpu 2kb data sram 2x usart 8khz nano ring 2x 16-bit timer gpio voltage monitor clock 80kb flash memory ir timer watchdog utility rom spi ir driver regulator maxq611 i 2 c block diagram note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maximintegrated. com/errata . maxq611 i nfrared remote control system-on-chip downloaded from: http:///
table of contents general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 block diagram ................................................................................ 1 absolute maximum ratings ...................................................................... 4 package thermal characteristics (note 1) .......................................................... 4 electrical characteristics ........................................................................ 4 typical operating characteristics ................................................................. 6 pin configuration .............................................................................. 7 pin description ................................................................................ 7 maxq611 detailed description .................................................................. 10 maxq20s architecture ........................................................................ 10 memory .................................................................................... 10 memory protection .................................................. ........................ 10 stack memory ................................................... ........................... 11 utility rom ................................................... ............................. 11 watchdog timer ............................................................................... 11 ir module .................................................................................. 12 timer/counter type b ......................................................................... 12 serial peripherals ............................................................................. 12 spi ................................................... .................................... 12 i 2 c ................................................... .................................... 12 usart ................................................... ................................ 13 general-purpose i/0 and external interrupts ............................................................................ 13 on-chip oscillator ............................................................................ 13 low-power operating modes ................................................................... 13 power-fail detection ................................................... ...................... 14 applications information ........................................................................ 14 grounds and bypassing ................................................... ................... 14 additional documentation ...................................................................... 18 development and technical support .............................................................. 19 ordering information/selector guide .............................................................. 19 package information .......................................................................... 19 appendix a .................................................................................. 20 maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 2 downloaded from: http:///
table of contents ( continued) list of figures list of tables figure 1. power-fail detection during normal operation .............................................. 14 figure 2. stop mode power-fail detection states with power- fail monitor enabled ......................... 16 figure 3. stop mode power-fail detection with power-fail mo nitor disabled .............................. 17 figure 4. series resistors (r s ) for protecting against high-voltage spikes ............................... 22 figure 5. i 2 c bus controller timing diagram ....................................................... 22 figure 6. spi master communication timing ....................................................... 24 figure 7. spi slave communication timing ........................................................ 24 figure 8. usart timing diagram ................................................................ 25 table 1. watchdog timer settings ................................................................. 11 table 2. maxq611 gpio and external interrupts .................................................... 13 table 3. power-fail detection states during normal operati on ......................................... 15 table 4. stop mode power-fail detection states with power-f ail monitor enabled .......................... 16 table 5. stop mode power-fail detection states with power-f ail monitor disabled ......................... 17 table 5. stop mode power-fail detection states with power-f ail monitor disabled (continued) .................................................................................. 18 i 2 c serial peripheral specifications ................................................... .......... 20 i 2 c serial peripheral specification (continued) ................................................... . 21 i 2 c serial diagrams ........................................................................... 22 serial peripheral interface (spi) specifications ................................................... . 23 spi timing diagrams .......................................................................... 24 usart mode 0 specifications ................................................... .............. 25 usart timing ............................................................................... 25 revision history .............................................................................. 26 maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 3 downloaded from: http:///
(all voltages with respect to gnd.) voltage range on v dd ......................................... -0.3v to +3.6v voltage range on any lead except v dd .... -0.3v to (v dd + 0.5v) continuous power dissipation (t a = +70c) tqfn (multilayer board) (derate 37mw/c above +70c) ................................ 2963mw operating temperature range ........................... -20c to +70c storage temperature range ............................ -65c to +150c soldering temperature (reflow) ....................................... +260c tqfn junction-to-ambient thermal resistance ( ja ) ........... 27c/w junction-to-case thermal resistance ( jc )..................1c/w (limits are 100% tested at t a = +25c and t a = +70c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units power supply voltage v dd v rst 3.6 v 1.8v internal regulator v reg18 1.62 1.80 1.98 v power-fail warning voltage v pfw1_70 pfwarncn = 0000 1.65 1.70 1.75 v v pfw1_80 pfwarncn = 0001 (default), gbd 1.75 1.80 1.85 v pfw1_90 pfwarncn = 0010, gbd 1.85 1.90 1.95 v pfw2_00 pfwarncn = 0011, gbd 1.94 2.00 2.06 v pfw2_10 pfwarncn = 0100, gbd 2.04 2.10 2.16 v pfw2_20 pfwarncn = 0101, gbd 2.14 2.20 2.26 v pfw2_30 pfwarncn = 0110, gbd 2.24 2.30 2.36 v pfw2_40 pfwarncn = 0111, gbd 2.33 2.40 2.47 v pfw2_50 pfwarncn = 1000, gbd 2.43 2.50 2.57 v pfw2_60 pfwarncn = 1001, gbd 2.53 2.60 2.67 v pfw2_70 pfwarncn = 1010, gbd 2.62 2.70 2.78 v pfw2_80 pfwarncn = 1011, gbd 2.72 2.80 2.88 v pfw2_90 pfwarncn = 1100, gbd 2.82 2.90 2.98 v pfw3_00 pfwarncn = 1101, gbd 2.91 3.00 3.09 v pfw3_10 pfwarncn = 1110, gbd 3.01 3.10 3.19 v pfw3_20 pfwarncn = 1111, gbd 3.11 3.20 3.29 power-fail reset voltage v rst 1.64 1.70 power-fail warning/reset offset v pfwrst pfwarncn = 0000, v pfw > v rst 30 mv power-on reset voltage v por monitors v dd 1.2 v ram data retention voltage v drv 1.0 v absolute maximum ratingspackage thermal characteristics (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . electrical characteristics maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 4 downloaded from: http:///
(limits are 100% tested at t a = +25c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units active current i dd_1 f sys = 12mhz, executing code from lash memory, all inputs connected to gnd/v dd , outputs do not source or sink current 2 3.7 ma stop mode current i s1 t a = +25c (power-fail off) 0.15 2.0 a t a = -20c to +70c (power-fail off) 0.15 8 i s2 t a = +25c (power-fail on) 22 31 a t a = -20c to +70c (power-fail on) 27.6 38 power consumption during power-on reset i por v dd < v por 100 na stop mode resume time t on 3/f nano + 1024/ f osc s clocks internal oscillator frequency f osc 12 mhz internal oscillator variability f osc_var t a = +25c, v dd = 1.8v 5% 0.5% t a = +25c, v dd = 1.8v 0.5% t a = -20c to +70c 1% system clock frequency f sys f osc /system clock divisor (1/2/4/8/256) 12 mhz system clock period t sys 1/f sys nanopower ring frequency f nano t a = +25c 3.0 12.0 20.0 khz t a = +25c, v dd = v por 1.7 2.4 khz general-purpose i/o and special functions input low voltage for irrx and all port pins v il v gnd 0.3 x v dd v input high voltage for irrx and all port pins v ih 0.7 x v dd v dd v input hysteresis (schmitt) v ihys v dd = 3.3v, t a = +25c 300 mv output low voltage for all port pins v ol v dd = 3.6v, i ol = 11ma 0.4 0.5 v v dd = 2.35v, i ol = 8ma 0.4 0.5 v dd = 1.8v, i ol = 4.5ma 0.4 0.5 output high voltage all port pins v oh ioh = -2ma v dd - 0.5 v dd v input/output pin capacitance for all port pins c io 15 pf input leakage current for all pins i l -100 +100 na electrical characteristics (continued) maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 5 downloaded from: http:///
(limits are 100% tested at t a = +25c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) (t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units input pullup resistor for reset , irrx, and all port pins r pu v dd = 3.0v, v ol = 0.4v 16 28 39 k v dd = 1.8v, v ol = 0.4v 18 31 43 ir module with internal amplifier input filter pulse-width reject t irrx_r 50 ns input filter pulse-width accept t irrx_a 300 ns irtx sink current i irtx v irtx 0.25v 200 ma wake-up timer wake-up timer interval t wakeup 1/ f nano 65,535/ f nano s flash memory flash memory controller clock frequency during program/ erase f fp f src /(fckdiv[3:0] + 1) must equal 1mhz, verify pfi = 0 before calling utility rom 1 mhz flash mass erase time t me 40 ms flash page erase time t erase 40 ms flash programming time per word t prog excluding utility rom overhead 40 s write/erase cycles 20,000 cycles data retention t a = +25c 100 years 0 50 100 150 200 250 300 350 400 450 0.0 0.5 1.0 1.5 2.0 i irtx (ma) v irtx (v) i irtx vs. v irtx (v dd = 1.8v) maximum setting (irout = 0x7f) toc01 nominal setting (irout = 0x4e) 0 50 100 150 200 250 300 350 400 450 500 0 1 2 3 4 i irtx (ma) v irtx (v) i irtx vs. v irtx (v dd = 3.6v) maximum setting (irout = 0x7f) toc02 nominal setting (irout = 0x4e) electrical characteristics (continued) typical operating characteristics maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 6 downloaded from: http:///
pin name function die tqfn power 24, 46 19, 41 v dd supply voltage. bypass to ground with a 4.7f capacitor. 22, 47 17, 20, 28, 42 gnd ground. connect directly to the ground plane. 23 18 reg18 1.8v regulator output. this pin must be connected to ground through a 1.0f external capacitor. the capacitor should be placed as close to this pin as possible. no devices other than the capacitor should be connected to this pin. ep exposed pad. connect to gnd or leave electrically unconnnected. reset 45 40 reset digital, active-low reset input/output. the device remains in reset while this bidirectional pin is in its active state. when the pin transitions to its inactive state the device exits reset and begins execution. external circuits must be able to sink in excess of 250a to overcome the internal pullup current source and take the pin to its active state. this pin should be left unconnected if the application does not provide a reset signal to the device. this pin is driven active as an output when an internal reset condition occurs. ir function 49 44 irrx ir receive input. this pin defaults to a high-impedance input after reset. 48 43 irtx ir transmit output. this pin defaults to a high-impedance input after reset. p0.1/rx0 r3.1/int9 p0.2/tx0 p0.3/rx1 p0.4/tx1 p0.5/tba0/tba1 p0.6/tbb0p0.7/tbb1 p1.0/int0 p3.0/int8 p0.0 1 2 3 4 5 6 7 8 9 10 11 p3.6/int14p3.7/int15 p2.6/tmsp2.7/tdo v dd gnd irtx irrx p2.5/tdi p2.4/tck 34 35 36 37 38 39 40 41 42 43 44 gndv dd reg18gnd p3.3/int11 p3.2/int10 p1.3/int3 p1.2/int2 p1.1/int1 p1.4/int4 p1.5/int5 22 21 20 19 18 17 16 15 14 13 12 p3.5/int13p3.4/int12 p2.1/miso gnd p2.0/mosi p1.7/int7 p1.6/int6 d.n.c. d.n.c. p2.2.sclk p2.3/ssel 33 32 31 30 29 28 27 26 25 24 23 44 tqfn-ep top view *exposed pad = gnd maxq611 + *ep reset pin coniguration pin description maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 7 downloaded from: http:///
pin description (continued) pin name function die tqfn general-purpose i/o and special functions 1 1 p0.0 p0.0: general-purpose i/o, port 0 pin 0 3 3 p0.1/rx0 p0.1: general purpose i/o, port 0 pin 1 rx0: usart 0 receive 5 5 p0.2/tx0 p0.2: general-purpose i/o, port 0 pin 2 tx0: usart 0 transmit 6 6 p0.3/rx1/ scl p0.3: general-purpose i/o, port 0 pin 3 rx1: usart 1 receive scl: i 2 c clock 8 7 p0.4/tx1/ sda p0.4: general-purpose i/o, port 0 pin 4 tx1: usart 1 transmit sda: i 2 c data 9 8 p0.5/tba0/ tba1 p0.5: general-purpose i/o, port 0 pin 5 tba0: timer b a0 tba1: timer b a1 11 9 p0.6/tbb0 p0.6: general-purpose i/o, port 0 pin 6 tbb0: timer b b0 13 10 p0.7/tbb1 p0.7: general-purpose i/o, port 0 pin 7 tbb1: timer b b1 15 11 p1.0/int0 p1.0: general-purpose i/o, port 1 pin 0 int0: external interrupt 0 17 12 p1.1/int1 p1.1: general-purpose i/o, port 1 pin 1 int1: external interrupt 1 18 13 p1.2/int2 p1.2: general-purpose i/o, port 1 pin 2 int2: external interrupt 2 19 14 p1.3/int3 p1.3: general-purpose i/o, port 1 pin 3 int3: external interrupt 3 25 21 p1.4/int4 p1.4: general-purpose i/o, port 1 pin 4 int4: external interrupt 4 28 22 p1.5/int5 p1.5: general-purpose i/o, port 1 pin 5 int5: external interrupt 5 31 25 p1.6/int6 p1.6: general-purpose i/o, port 1 pin 6 int6: external interrupt 6 32 26 p1.7/int7 p1.7: general-purpose i/o, port 1 pin 7 int7: external interrupt 7 33 27 p2.0/mosi p2.0: general-purpose i/o, port 2 pin 0 mosi: spi master-out/slave-in 34 29 p2.1/miso p2.1: general-purpose i/o, port 2 pin 1 miso: spi master-in/slave-out 37 32 p2.2/sclk p2.2: general-purpose i/o, port 2 pin 2 sclk: spi clock maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 8 downloaded from: http:///
pin description (continued) pin name function die tqfn 38 33 p2.3/ssel p2.3: general-purpose i/o, port 2 pin 3 ssel: spi slave select 39 34 p2.4/tck p2.4: general-purpose i/o, port 2 pin 4 tck: jtag clock. the por default for the pd2.4 bit activates the weak pullup. 40 35 p2.5/tdi p2.5: general-purpose i/o, port 2 pin 5 tdi: jtag data in. the por default for the pd2.5 bit activates the weak pullup. 43 38 p2.6/tms p2.6: general-purpose i/o, port 2 pin 6 tms: jtag test mode select. the por default for the pd2.6 bit activates the weak pullup. 44 39 p2.7/tdo p2.7: general-purpose i/o, port 2 pin 7 tdo: jtag data output. the por default for the pd2.7 bit activates the weak pullup. 2 2 p3.0/int8 p3.0: general-purpose i/o, port 3 pin 0 int8: external interrupt 8 4 4 p3.1/int9 p3.1: general-purpose i/o, port 3 pin 1 int9: external interrupt 9 20 15 p3.2/int10 p3.2: general-purpose i/o, port 3 pin 2 int10: external interrupt 10 21 16 p3.3/int11 p3.3: general-purpose i/o, port 3 pin 3 int11: external interrupt 11 35 30 p3.4/int12 p3.4: general-purpose i/o, port 3 pin 4 int12: external interrupt 12 36 31 p3.5/int13 p3.5: general-purpose i/o, port 3 pin 5 int13: external interrupt 13 41 36 p3.6/int14 p3.6: general-purpose i/o, port 3 pin 6 int14: external interrupt 14 42 37 p3.7/int15 p3.7: general-purpose i/o, port 3 pin 7 int15: external interrupt 15 7 p4.0 p4.0: general-purpose i/o, port 4 pin 0 10 p4.1 p4.1: general-purpose i/o, port 4 pin 1 12 p4.2 p4.2: general-purpose i/o, port 4 pin 2 14 p4.3 p4.3: general-purpose i/o, port 4 pin 3 16 p4.4 p4.4: general-purpose i/o, port 4 pin 4 26 p4.5 p4.5: general-purpose i/o, port 4 pin 5 no connections 23, 24 d.n.c. do not connect. internally connected. 27, 29, 30 n.c. do not connect maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 9 downloaded from: http:///
maxq611 detailed description the device provides integrated, low-cost solutions that simplify the design of ir communications equipment such as universal remote controls. the internal 12mhz oscillator requires no external components. standard features include the highly optimized, single-cycle, maxq, 16-bit risc core; 80kb flash memory; 2kb data ram; soft stack; 16 general-purpose registers; and three data pointers. the maxq core has the industrys best mips/ ma rating, allowing developers to achieve the same per - formance as competing microcontrollers at substantially lower clock rates. application-specific peripherals include flexible timers for generating ir carrier frequencies and modulation. a high-current ir drive pin operates with an internal receiver amplifier without external components. it also includes general-purpose i/o pins ideal for keypad matrix input, and a power-fail-detection circuit to notify the application when the supply voltage is nearing the microcontrollers minimum operating voltage. the combination of high-performance instructions and ultra-low stop-mode current increases battery life over competing microcontrollers. an integrated por circuit with brownout support resets the device to a known condition following a power-up cycle or brownout condition. additionally, a power-fail warning flag is set, and a power- fail interrupt can be generated when the system voltage falls below the power-fail warning voltage, v pfw . the power-fail warning feature allows the application to notify the user that the system supply is low and appropriate action should be taken. maxq20s architecture the low-power maxq20s pipelined core supports the harvard memory architecture with separate 16-bit program and data address busses. most of the 16-bit instruction words execute in a single clock cycle with performance approaching 1mips per mhz. the 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. the accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (alu). a configurable soft stack supports program flow. execution of instructions is triggered by data trans - fer between functional register modules or between a functional register module and memory. because data movement involves only source and destination modules, circuit switching activities are limited to active modules only. this approach localizes power dissipation and minimizes switching noise. the maxq instruction set is highly orthogonal. all arithmetical and logical operations can use any register in conjunction with the accumulator. data can be arranged in 8 or 16 bits, and movement is supported between any two registers. memory is accessed through specific data- pointer registers with autoincrement/decrement support. memory the microcontroller incorporates several memory types: ? 80kb flash memory ? 2kb sram data memory ? dedicated utility rom ? soft stack memory protection the optional memory-protection feature segments code memory into three areas with different access privileges. this allows unique code segments to be loaded at differ - ent steps in the manufacturing process, while restricting access to higher-privilege segments that might have been loaded earlier in the process. the memory protection segments are: ? system (highest privilege) ? user-loader (medium privilege) ? user-application (lowest privilege) code in the system area is typically loaded by the oem, and can be read/write protected from code executing in lower privilege segments. in a similar manner, the user- loader segment can be read/write protected from code executing in the user-application area. maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 10 downloaded from: http:///
stack memory the maxq20s core provides a soft stack that can be used to store program return addresses (for subroutine calls and interrupt handling) and other general-purpose data. this soft stack is located in data memory, which means that the sram data memory must be shared between the soft stack and general-purpose application data storage. however, the location and size of the soft stack is determined by the user, providing maximum flex - ibility when allocating resources for a particular applica - tion. the stack is used automatically by the processor when the call, ret, and reti instructions are executed and when an interrupt is serviced. an application can also store and retrieve values explicitly using the stack by means of the push, pop, and popi instructions. the sp pointer indicates the current top of the stack, which initializes by default to the top of the sram data memory. as values are pushed onto the stack, the sp pointer decrements, which means that the stack grows downward towards the bottom (lowest address) of the data memory. popping values off the stack causes the sp pointer value to increase. utility rom the utility rom is located in program space beginning at address 8000h. this rom includes the following routines: ? production test routines (internal memory tests, memory loader, etc.), which are used for internal testing only, and are generally of no use to the end- application developer ? user-callable routines for buffer copying and fast table lookup following any reset, execution begins in the utility rom at address 8000h. at this point, unless test mode has been invoked (which requires special programming through the jtag interface), the utility rom in the device always automatically jumps to location 0000h, which is the begin - ning of user application code. watchdog timer the internal watchdog timer greatly increases system reliability. the timer resets the device if software execution is disturbed. the watchdog timer is a free-running counter designed to be periodically reset by the application software. if software is operating correctly, the counter is periodically reset and never reaches its maximum count. however, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. this protects the system against electrical noise or electrostatic discharge (esd) upsets that could cause uncontrolled processor operation. the internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. the watchdog timer functions as the source of both the watchdog timer timeout and the watchdog timer reset. the timeout period is user-programmable using the wd bits as shown in table 1. an interrupt is generated when the timeout period expires if the interrupt is enabled. all watchdog timer resets follow the programmed interrupt timeouts by 512 system clock cycles. if the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. see table 1 . table 1. watchdog timer settings wd (cd = 00) period interrupt (f sys = 12mhz) reset (f sys = 12mhz) 00 2 15 /f sys 2.7ms 2.7ms + 42.7s 01 2 18 /f sys 21.9ms 21.9ms + 42.7s 10 2 21 /f sys 174.7ms 147.7ms + 42.7s 11 2 24 /f sys 1.4s 1.4s + 42.7s maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 11 downloaded from: http:///
ir module the ir module provides low-speed communication capability for remote control applications. dedicated timers simplify implementation and maximize application performance. the device is used in the traditional learning circuit mode, with the receiver accepting digital input. the peripheral provides the following features: ? transmit and receive (code learning) modes ? automatic carrier generation/modulation ? pulse-width glitch filter improves noise immunity ? configurable high-current driver supports multiple led types ? supports receiver currents up 8a ? transmit frequency up to 115.2khz one instance of the ir peripheral is provided. timer/counter type b timer/counter type b is an enhanced 16-bit timer that pro - vides input clock prescaling and pulse-width modulation (pwm) through set/reset/compare output functionality. it provides the following features: ? 16-bit timer/counter ? 16-bit up/down autoreload ? counter function of external pulse ? 16-bit timer with capture ? 16-bit timer with compare ? set/reset/toggle output state on comparator match ? clock output mode ? input/output enhancements for pulse-width modulation ? timer input prescale option two instances of the peripheral are provided. serial peripherals spi the serial peripheral interface (spi) is a four-wire bus providing fast, synchronous, full-duplex communications between devices. the peripheral provides the following features: ? master or slave mode support ? maximum spi master transfer rate is f sys /2 ? maximum spi slave transfer rate is f sys /4 ? 8 or 16-bit data length ? programmable clock phase and polarity ? robust fault detection: mode fault detection write collision detection receiver overrun detection ? programmable slave select pin polarity one instance of the spi peripheral is provided. i 2 c the i 2 c bus is a bidirectional, two-wire serial bus that provides a medium-speed communications network. it can operate as a one-to-one, one-to-many or many-to- many communications medium. it provides the following features: ? master or slave mode operation ? information transferal over a serial data circuit (sda) and serial clock circuit (scl) ? supports standard (7-bit) addressing ? support for clock stretching to allow slower slave devices to operate on higher speed busses ? support for multiple transfer rates: standard mode: 100kbps fast mode: 400kbps fast mode plus: 1mbps ? on-chip filter to reject spikes on the data circuit. ? receiver fifo depth of 2 bytes ? transmitter fifo depth of 2 bytes one instance of the i 2 c peripheral is provided. maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 12 downloaded from: http:///
usart the universal synchronous/asynchronous receiver/trans - mitter (usart) peripheral is a two-wire, serial interface that provides fast communication between devices. it provides the following features: ? full-duplex operation for asynchronous data transfers ? half-duplex operation for synchronous data transfers ? programmable interrupt when transmit or receive data operation completes ? independent, programmable baud-rate generator ? 9th data bit can be fixed 0, 1, or used as a software parity bit ? start and stop bits used in asynchronous modes ? maximum frequency in synchronous mode: f src /4 ? maximum frequency in asynchronous mode: f src /2 21 two instances of the usart peripheral are provided. general-purpose i/0 and external interrupts port pins are provided for general-purpose i/o (gpio) with the following features: ? cmos output drivers ? schmitt trigger inputs ? optional weak pullup to v dd when operating in input mode table 2 lists the available gpio and external interrupts. many gpio pins share special functions with device peripherals and external interrupts. these special functions are listed in the pin description section, and described in the relevant users guide section. on-chip oscillator an internal 12mhz oscillator is provided that requires no external components, thereby reducing system cost, pcb area, and radiated emi. low-power operating modes the lowest power mode of operation is stop mode. in this mode, cpu state and memories are preserved, but the cpu is not actively running. wake-up sources include external i/o interrupts, the power-fail warn - ing interrupt, wake-up timer, or a power-fail reset. any time the microcontroller is in a state where code does not need to be executed, the user software can put the device into stop mode. the nanopower ring oscillator is an internal ultra-low-power 8khz ring oscillator that can drive a wake-up timer that exits stop mode. the wake-up timer is programmable by software in steps of 125s up to approximately 8s. the power-fail monitor is always active during normal operation. during stop mode, the power-fail monitor can be enabled using the power-fail monitor bit (pfd). it is disabled (pfd = 1) by default after a por. if disabled, the v dd < v rst condition does not invoke a reset state. regardless of the pfd bit, the v dd < v por condition generates a por in stop mode. regardless of the state of the pfd bit, the power-fail monitor is enabled immediately prior to exiting stop mode. if a power-fail warning condition (v dd < v pfw ) is then detected, the power-fail interrupt flag is set on stop mode exit. if a power-fail condition is detected (v dd < v rst ), the device remains in reset and drives the reset pin low. table 2. maxq611 gpio and external interrupts package gpio external interrupts 44 tqfn-ep p0[7:0]p1[7:0] p2[7:0] p3[7:0] int[15:0] bare die p0[7:0]p1[7:0] p2[7:0] p3[7:0] p4[5:0] int[15:0] maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 13 downloaded from: http:///
power-fail detection figure 1 , figure 2 , and figure 3 show the power-fail detection and response during normal and stop-mode operation. if a reset is caused by a power-fail, the power- fail monitor can be set to one of the following intervals: ? always oncontinuous monitoring ? 2 11 nanopower ring oscillator clocks (~256ms) ? 2 12 nanopower ring oscillator clocks (~512ms) ? 2 13 nanopower ring oscillator clocks (~1.024s) in the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two nanopower ring-oscillator cycles. if v dd > v rst during detection, v dd is monitored for an additional nanopower ring-oscillator period. if v dd remains above v rst for the third nanopower ring period, the cpu exits the reset state and resumes normal operation from utility rom at 8000h after satisfying the crystal warmup period. the voltage (v pfw ) below which a power-fail warning is generated is user configurable through the pfwarncn bits. see the electrical characteristics table for the v pfw options and corresponding pfwarncn values. if the reset pin is being driven active by an external source, or a watchdog timer reset occurs, the power-fail, internal regulator, and crystal oscillator (if present) remain on during the reset event. the reset is exited in less than 20 f osc cycles after the reset source is removed. applications information the low-power, high-performance risc architecture of this device makes it an excellent fit for many portable or battery-powered applications. it is ideally suited for appli - cations such as universal remote controls that require the cost-effective integration of ir transmit/receive capability. grounds and bypassing careful pcb layout significantly minimizes system-level digital noise that could interact with the microcontroller or peripheral components. the use of multilayer boards is essential to allow the use of dedicated power planes. the area under any digital components should be a con - tinuous ground plane if possible. keep bypass capacitor leads short for best noise rejection and place the capaci - tors as close as possible to the leads of the devices. figure 1. power-fail detection during normal operation a b c d f g h i e v dd v pfw v rst v por internal reset (active high) t < t pfw t t pfw t t pfw t t pfw maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 14 downloaded from: http:///
table 3. power-fail detection states during normal operation state power-fail internal regulator crystal oscillator sram retention comments a on off off v dd < v por . b on on on v por < v dd < v rst . crystal warmup time, t xtal_rdy . cpu held in reset. c on on on v dd > v rst . cpu normal operation. d on on on power drop too short.power-fail not detected. e on on on v rst < v dd < v pfw . pfi is set when v rst < v dd < v pfw and maintains this state for at least t pfw , at which time a power-fail interrupt is generated (if enabled). cpu continues normal operation. f on (periodically) off off yes v por < v dd < v rst . power-fail detected.cpu goes into reset. power-fail monitor turns on periodically. g on on on v dd > v rst . crystal warmup time, t xtal_rdy . cpu resumes normal operation from 8000h. h on (periodically) off off yes v por < v dd < v rst . power-fail detected.cpu goes into reset. power-fail monitor turns on periodically. i off off off v dd < v por . device held in reset. no operation allowed. maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 15 downloaded from: http:///
figure 2. stop mode power-fail detection states with power-fail monitor enabled table 4. stop mode power-fail detection states with power-fail monitor enabled state power-fail internal regulator crystal oscillator sram retention comments a on off off yes application enters stop mode.v dd > v rst . cpu in stop mode. b on off off yes power drop too short.power-fail not detected. c on on on yes v rst < v dd < v pfw . power-fail warning detected. turn on regulator and crystal. crystal warmup time, t xtal_rdy . exit stop mode. d on off off yes application enters stop mode.v dd > v rst . cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst . power-fail detected.cpu goes into reset. power-fail monitor turns on periodically. f off off off v dd < v por . device held in reset. no operation allowed. v pfw v rst v por a b c d e f v dd t < t pfw t t pfw t t pfw stop internal reset (active high) maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 16 downloaded from: http:///
figure 3. stop mode power-fail detection with power-fail monitor disabled table 5. stop mode power-fail detection states with power-fail monitor disabled state power-fail internal regulator crystal oscillator sram retention comments a off off off yes application enters stop mode.v dd > v rst . cpu in stop mode. b off off off yes v dd < v pfw . power-fail not detected because power-fail monitor is disabled. c on on on yes v rst < v dd < v pfw . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power-fail warning, and sets the power-fail interrupt lag. turn on regulator and crystal. crystal warmup time, t xtal_rdy . on stop mode exit, cpu vectors to the higher priority of power-fail and the interrupt that causes stop mode exit. v pfw v rst v por v dd a b c d e f stop interrupt internal reset (active high) maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 17 downloaded from: http:///
cmos design guidelines for any semiconductor require that no pin be taken above v dd or below gnd. violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (unintentional modification of memory contents). voltage spikes above or below the devices absolute maximum ratings can potentially cause a devastating ic latchup. microcontrollers commonly experience negative voltage spikes through either their power pins or general-purpose i/o pins. negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. devices such as keypads can conduct electrostatic discharges directly into the micro - controller and seriously damage the device. system designers must protect components against these transients that can corrupt system memory. additional documentation engineers must have the following documents to fully use this device: ? this data sheet, containing pin descriptions, feature overviews, and electrical specifications. ? the device-appropriate user guide, containing detailed information and programming guidelines for core features and peripherals. ? errata sheets for specific revisions noting deviations from published specifications. for information regarding these documents, visit technical support at support.maximintegrated.com/micro . table 5. stop mode power-fail detection states with power-fail monitor disabled (continued) state power-fail internal regulator crystal oscillator sram retention comments d off off off yes application enters stop mode.v dd > v rst . cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power-fail, and puts cpu in reset. power-fail monitor is turned on periodically. f off off off v dd < v por . device held in reset. no operation allowed. maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 18 downloaded from: http:///
development and technical support contact technical support for information about highly versatile, affordable development tools, available from maxim integrated and third-party vendors. ? evaluation kits ? compilers ? integrated development environments (ides) ? usb interface modules for programming and debugging for technical support, go to support.maximintegrated.com/micro . note: the 4-digit suffix -xxxx indicates a device preprogrammed at maxim integrated with proprietary customer-supplied software. for more information on factory preprogramming of this device, contact maxim integrated at support.maximintegrated.com/micro . +denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *future productcontact factory for availability. **ep = exposed pad. part temp range operating voltage (v) program memory (kb) data memory (kb) gpio pin-package maxq611j-xxxx+t* -20c to +70c 1.70 to 3.6 80 flash 2 32 44 tqfn-ep** maxq611x-xxxx+ -20c to +70c 1.70 to 3.6 80 flash 2 38 bare die package type package code outline no. land pattern no. 44 tqfn-ep t4477+3c 21-0144 90-0128 ordering information/selector guide package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 19 downloaded from: http:///
parameter symbol conditions standard mode fast mode units min max min max input low voltage v il_i2c supply voltages that mismatch i 2 c bus levels must relate input levels to the r p pullup voltage -0.5 0.3 x v dd -0.5 0.3 x v dd v input high voltage v ih_i2c supply voltages that mismatch i 2 c bus levels must relate input levels to the r p pullup voltage 0.7 x v dd 0.7 x v dd v dd + 0.5v v input hysteresis (schmitt) v ihys_i2c v dd > 2v 0.05 x v dd v output logic-low (open drain or open collector) v ol_i2c v dd > 2v, 3ma sink current 0 0.4 0 0.4 v capacitive load for each bus line c b 400 400 pf output fall time from v ih_min to v il_max with bus capacitance from 10pf to 400pf t of_i2c t r/f_i2c exceeds t of_i2c , which permits rs to be connected as shown in figure 250 20 + 0.1c b 250 ns pulse width of spike filtering that must be suppressed by input filter t sp_i2c 0 50 ns input current on i/o i in_i2c input voltage from 0.1 x v dd to 0.9 x v dd -10 +10 -10 +10 f a i/o capacitance c io_i2c 10 10 pf i 2 c bus operating frequency f i2c 0 100 0 400 khz system frequency f sys 0.90 3.60 mhz i 2 c bit rate f i2c f sys /8 f sys /8 hz hold time after (repeated) start t hd:sta 4.0 0.6 f s clock low period t low_i2c 4.7 1.3 f s clock high period t high_i2c 4.0 0.6 f s setup time for repeated start t su:sta 4.7 0.6 f s appendix a i 2 c serial peripheral speciications (see figure 4 and figure 5 .) maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 20 downloaded from: http:///
parameter symbol conditions standard mode fast mode units min max min max hold time for data t hd:dat a device must internally provide a hold time of at least 300ns for v ih_i2c(min) to bridge the undefined region of the falling edge of scl. the maximum t hd:dat needs to be met only if the device does not stretch the scl low period 0 3.45 0 0.9 f s setup time for data t su:dat a fast-mode i 2 c bus device can be used in a standard-mode i 2 c bus system; if such a device does not stretch the low period of the scl signal, it must output the next data bit to the sda line t r_i2c(max) + t su:dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c specification) before the scl line is released 250 100 ns sda/scl fall time t f_i2c 300 20 + 0.1c b 300 ns sda/scl rise time t r_i2c 1000 20 + 0.1c b 300 ns setup time for stop t su:sto 4.0 0.6 f s bus free time between stop and start t buf 4.7 1.3 f s noise margin at the low level for each connected device (including hysteresis) v nl_i2c 0.1 x v dd 0.1 x v dd v noise margin at the low level for each connected device (including hysteresis) v nh_i2c 0.2 x v dd 0.2 x v dd v i 2 c serial peripheral speciication (continued) (see figure 4 and figure 5 .) maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 21 downloaded from: http:///
figure 4. series resistors (r s ) for protecting against high-voltage spikes figure 5. i 2 c bus controller timing diagram sda scl r s r s i 2 c device r s r s i 2 c device r p r p v dd maxq611 sdascl s sr p s t f_i2c t r_i2c t low_i2c t high_i2c t hd:sta t su:dat t su:sta t su:sto t buf t hd:dat note: timing referenced to v ih_i2c(min) and v il_i2c(max). i 2 c serial diagrams maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 22 downloaded from: http:///
parameter symbol conditions min typ max units spi master frequency f mck f sys /2 mhz spi slave frequency f sck f sys /4 mhz spi master period t mck 1/f mck spi slave period t sck 1/f sck sclk output pulse-width high/low t mch , t mcl t mck /2 - 35 ns mosi output hold time after sclk sample edge t moh t mck /2 - 35 ns mosi output valid to sample edge t mov t mck /2 - 35 ns miso input valid to sclk sample edge rise/fall setup t mis 35 ns miso input to sclk sample edge rise/fall hold t mih 0 ns sclk input pulse-width high/low t sch , t scl t sck /2 ns ssel active to first shift edge t sse 50 ns mosi input to sclk sample edge rise/fall setup t sis 35 ns mosi input from sclk sample edge transition hold t sih 35 ns miso output valid after sclk shift edge transition t sov 70 ns sclk inactive to ssel rising t sd 35 ns serial peripheral interface (spi) speciications(see figure 6 and figure 7 .) maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 23 downloaded from: http:///
figure 6. spi master communication timing figure 7. spi slave communication timing ssel (active low) sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 mosimiso lsb lsb shift sample shift sample t mck t mch t moh t mis t mov t rf t mlh t mih t mcl msb msb-1 msb msb-1 shift sample shift sample sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 mosimiso t sse t sck t sch t scl t sis t sov t slh t ssh t sd t rf t sih msb msb-1 msb msb-1 lsb lsb ssel (active low) spi timing diagrams maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 24 downloaded from: http:///
figure 8. usart timing diagram parameter symbol conditions min typ max units usart clock period t clcl 1/f sys txd clock period t xlxl sm2 = 0 12t clcl ns sm2 = 1 4t clcl ns txd clock high time t xhxl sm2 = 0 3t clcl ns sm2 = 1 2t clcl ns rxd output data valid to txd clock rising edge t qvxh sm2 = 0 10t clcl ns sm2 = 1 3t clcl ns rxd output data hold from txd clock rising edge t xhqh sm2 = 0 2t clcl ns sm2 = 1 t clcl ns rxd input data valid to txd clock rising edge t dvxh sm2 = 0 t clcl ns sm2 = 1 t clcl ns rxd input data hold after txd clock rising edge t xhdh sm2 = 0 t clcl ns sm2 = 1 t clcl ns t xlxl t xhxl t dvxh t xhdh t qvxh t xhqh txd clock rxd input rxd output bit x bit x bit x + 1 usart timing usart mode 0 speciications(see figure 8 .) maxq611 infrared remote control system-on-chip www.maximintegrated.com maxim integrated 25 downloaded from: http:///
revision number revision date description pages changed 0 6/14 initial release 1 12/14 updated general description and beneits and features sections ; added typical operating characteristics; replaced table 2; added new figures 1C4 and renumbered remaining igures; updated ir module section; corrected part number in figure 9 1, 4, 6C9, 13 revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. maxq611 infrared remote control system-on-chip ? 2014 maxim integrated products, inc. 26 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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